Turbo decoder, 3GPP compatible

Salamander Error Correction

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SAL20101D -- 3GPP compatible Turbo decoder

The SAL20101D is a decoder of the turbo code specified in the 3GPP specification TS 25.212.

The basic code is an 8-state (constraint length 4) Recursive Systematic Convolutional code which is well suited to channels with predominantly Gaussian noise.

The decoder operates twice per iteration on the input data frame. One half-iteration operates on the data in natural order and the other operates on a permuted version of the input data. The permutation is accomplished as described in detail in the 3GPP specification using an interleaver module.

The device uses 6-bit inputs and a full log-MAP SISO decoder module to ensure superior error correction performance.

Benefits

3GPP TS 25.212 compatible

6-bit 2's compliment, signed-magnitude, or unsigned binary input

full log-MAP functionality

Simple handshake protocol for reliable interfacing

Fully synchronous design

Medium area, medium speed ~ 3 Mbps operation

Full 3GPP compliant hardware interleaver. No external calculation required.

Interleaver frame size selectable on a frame-by-frame basis

All defined block sizes supported

Programmable number of iterations

Documentation

Datasheet

Ordering Information

SAL20101D-v

HDL license -- Verilog source code

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SAL20101D-x

Netlist license -- Xilinx netlist

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Contact us at sales@salamander-ecc.com for more information, or to request a custom designed solution.

Reed-Solomon, Viterbi, and Turbo Codes. Salamander Error Correction specializes in the design and marketing of Verilog IP modules for Forward Error Correction.

Salamander Error Correction

5330 Carroll Canyon Rd

San Diego, CA 92121

(858) 373-2112

Fax: (858) 373-1224

sales@salamander-ecc.com